- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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Ultra-High-Speed 2:1 Digital Selector and Plasmonic Modulator IM/DD Transmitter Operating at 222 GBaud for Intra-Datacenter Applications
摘要： This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimental I-V characteristics from irradiated devices. The modeling approach is suitable for simulating TID and aging effects in advanced MOS devices and ICs, and is compatible with modern MOSFET compact modeling techniques. A circuit-level demonstration is given for TID and aging effects in SRAM cells.
关键词： compact modeling,SOI,ionizing radiation,semiconductor devices,MOSFET,Aging effects
更新于2025-09-23 15:19:57
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[IEEE 2020 10th Annual Computing and Communication Workshop and Conference (CCWC) - Las Vegas, NV, USA (2020.1.6-2020.1.8)] 2020 10th Annual Computing and Communication Workshop and Conference (CCWC) - DFB Laser Chip Defect Detection Based on Successive Subspace Learning
摘要： This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimental I-V characteristics from irradiated devices. The modeling approach is suitable for simulating TID and aging effects in advanced MOS devices and ICs, and is compatible with modern MOSFET compact modeling techniques. A circuit-level demonstration is given for TID and aging effects in SRAM cells.
关键词： MOSFET,SOI,semiconductor devices,compact modeling,ionizing radiation,Aging effects
更新于2025-09-23 15:19:57
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[IEEE 2019 6th International Conference on Advanced Control Circuits and Systems (ACCS) & 2019 5th International Conference on New Paradigms in Electronics & information Technology (PEIT) - Hurgada, Egypt (2019.11.17-2019.11.20)] 2019 6th International Conference on Advanced Control Circuits and Systems (ACCS) & 2019 5th International Conference on New Paradigms in Electronics & information Technology (PEIT) - Compact Adiabatic Taper for SOI Waveguide
摘要： In this paper, we present a novel design of an adiabatic compact taper which can be used as a converter between a grating coupler and a single-mode optical fiber at 1550 nm wavelength. The proposed taper in this paper is coupling the light between a wide grating coupler with width 15μ and nanophotonic waveguide with width 500nm. Besides, the length of the proposed design is 22μm. Therefore, it is a compact design as it has a small footprint which leads to high efficiency and low costs in fabrication. The coupling efficiency is around 92%.
关键词： SOI,Coupling,Silicon Photonics
更新于2025-09-23 15:19:57
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[IEEE 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) - Grenoble, France (2019.4.1-2019.4.3)] 2019 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS) - Thin Si channel Back Enhanced (BE) SOI pMOSFET Photodetector under different bias conditions
摘要： This paper explores the light sensitivity of the new Back Enhanced (BE) SOI MOSFET. This new device has a reconfigurable operation (can work both like p- and n-type transistors depending on the back gate bias) and an extremely simple fabrication process, without any intentional doping steps and a planar structure. Two different bias conditions to detect light will be compared aiming a higher difference of drain current (sensitivity). The first one is based on better conduction due to the optical generation and the other thanks to the threshold voltage variation. Experimental analysis were performed and the results were compared for different bias conditions.
关键词： reconfigurable devices,BE SOI pMOSFET,light sensor
更新于2025-09-23 15:19:57
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Device Physics, Modeling, Technology, and Analysis for Silicon MESFET || Modeling of Classical SOI MESFET
摘要： Since the advent of the ?rst integrated circuit, the downscaling trend has led to extensive progress regarding cost, performance, and level of integration. It is well known that development in the level of integration is achieved by continuous reduction of the minimum size of electronic components. However, since downscaling has encroached on submicron territory, some undesirable effects have begun to pull down the performance of transistors. Also, the technological problems related to shrinking junctions and growing high-integrity thin oxide layer are apparent. Hence, the reduction in physical dimensions needs to be concurrent with some other alterations like increasing of doping levels, reducing of insulator thickness, and decreasing of junction depth to degrade the second-order effects related to downscaling. When gate lengths are scaled and doping levels are increased, electric ?elds tend to rise. The higher electric ?eld, in small geometry devices, emitted the energetic carriers into the gate oxide layer and caused a shift in threshold voltage and therefore the reduction of transconductance with time (hot carrier effect). This problem can be lessened by reducing the junction electric ?eld which is obtained by the reduction of the source and drain doping concentrations. But, low-doped regions, especially in small geometry devices, bring some other disadvantages like the high contact resistance. Also, lightly doped drain (LDD) MOS devices are introduced to repress the hot carrier effects. In these devices, introducing a narrow, lightly doped n-type region between the channel and the drain and source areas, the doping pro?le of the drain and source is modi?ed. As a result, the electric ?eld in the pinch-off region and thus the hot carrier effect and also the impact ionization are reduced. However, LDD MOSFETs have some drawbacks including the degradation of the current drive due to the increasing resistance and more processing complexity of the device manufacturing. Another challenge of dimension downscaling relates to the ultra-thin oxide layer. The growing of high-quality and low-defect thin oxides is dif?cult. Moreover, quantum mechanical direct tunneling (QMDT) is an important disadvantage in the ultra-thin gate oxide which remarkably reduces the device performance. The last challenge is related to the junction depth scaling. The fact is that due to the various technological reasons, the junction depth has not been scaled pretty with scaling of channel lengths.
关键词： quantum mechanical direct tunneling,LDD MOSFETs,SOI MESFET,hot carrier effect,downscaling
更新于2025-09-23 15:19:57
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[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Towards a Suburban Quantum Network Link
摘要： This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimental I-V characteristics from irradiated devices. The modeling approach is suitable for simulating TID and aging effects in advanced MOS devices and ICs, and is compatible with modern MOSFET compact modeling techniques. A circuit-level demonstration is given for TID and aging effects in SRAM cells.
关键词： compact modeling,SOI,ionizing radiation,semiconductor devices,MOSFET,Aging effects
更新于2025-09-19 17:13:59
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[IEEE 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - Chicago, IL, USA (2019.6.16-2019.6.21)] 2019 IEEE 46th Photovoltaic Specialists Conference (PVSC) - UV exposure: a novel processing method to fabricate nanowire solar cells
摘要： This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimental I-V characteristics from irradiated devices. The modeling approach is suitable for simulating TID and aging effects in advanced MOS devices and ICs, and is compatible with modern MOSFET compact modeling techniques. A circuit-level demonstration is given for TID and aging effects in SRAM cells.
关键词： MOSFET,SOI,semiconductor devices,compact modeling,ionizing radiation,Aging effects
更新于2025-09-19 17:13:59
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[IEEE 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Munich, Germany (2019.6.23-2019.6.27)] 2019 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC) - Integrated Plasmonic Tweezers for Efficient Nanoparticle Trapping
摘要： Optical tweezing system arises from light-matter interactions which provide light driving force capable of directing a particle to a potential well and to maintain it in a stable position [1]. Recently it has been shown that the use of plasmonic structures makes it possible to overcome the problems of diffraction limit in dielectric since these structures are able to concentrate light in deep subwavelength volumes. The excitation of localized surface plasmons (LSPs) at metal nanoparticles (MNPs) can significantly amplify the electromagnetic field in the vicinity of the nanoantennas, providing an optical gradient force for near-field optical trapping. In such a way, by introducing plasmonic resonators inside tweezing systems, very deep and narrow potential well can be tailored to achieve optical tweezing down to subwavelength particles [2]. In references [3,4], we have numerically shown that the strong coupling occurring between a SOI waveguide and a gold MNP chain allows conceiving surface plasmon-based nanotweezers with efficient trapping of dielectric nanobeads, having radii down to 50 nm. In this contribution, we experimentally do the demonstration of trapping of dielectric nanobead with such structures. Fig. 1(a) and Fig. 1(b) present a general sketch of the system and a SEM image of a fabricated structure composed of 20 MNPs placed on top of a monomode SOI waveguide. The SOI waveguide has a height hSi=220 nm and a width wSi =500 nm. The MNPs are gold elliptic nanocylinders with radii rx=50 nm, ry=100 nm and a thickness h=30 nm. The gap g between two successive MNPs is close to 30 nm. Optical transmittance characterizations show that the structure presents a resonance around 1530 nm as shown in Fig. 1(c). We have shown that this structure, submerged in water (Fig. 1(d)), is able to trap small spherical beads of polystyrene having a radius r =500, 250 and 100 nm, with an incident nominal laser power of 6 mW. By considering thermodynamic equilibrium of the nanobead with the environment, we have used Boltzmann statistics to determine the stiffness of the trapping system, by recording the number of occurrences of positions occupied by the bead (Fig. 1(e)). Fig. 1(f) shows the potential energy well determined from the statistical position on a polystyrene bead with a diameter of 1 μm. We have determined stiffness kx=(5,10 ± 0,67).10-1 fN?nm-1?W-1 and ky = (2,61 ± 0,35) fN?nm-1?W-1, respectively along the waveguide direction x and along y.
关键词： SOI waveguide,nanoparticle trapping,optical tweezing,plasmonic tweezers,plasmonic resonators
更新于2025-09-19 17:13:59
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A Time-of-Flight Range Sensor Using Four-Tap Lock-In Pixels with High near Infrared Sensitivity for LiDAR Applications
摘要： In this paper, a back-illuminated (BSI) time-of-flight (TOF) sensor using 0.2 μm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) technology is developed for long-range laser imaging detection and ranging (LiDAR) application. A 200 μm-thick bulk silicon in the SOI substrate is fully depleted by applying high negative voltage at the backside for higher quantum efficiency (QE) in a near-infrared (NIR) region. The proposed SOI-based four-tap charge modulator achieves a high-speed charge modulation and high modulation contrast of 71% in a NIR region. In addition, in-pixel drain function is used for short-pulse TOF measurements. A distance measurement up to 27 m is carried out with +1.8~?3.0% linearity error and range resolution of 4.5 cm in outdoor conditions. The measured QE of 55% is attained at 940 nm which is suitable for outdoor use due to the reduced spectral components of solar radiation.
关键词： CMOS image sensor,time-of-flight,backside-illumination,SOI detector,lock-in pixel
更新于2025-09-16 10:30:52
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Introducing Waveguide Loss: Another Way to Realize a High-Sensitivity Microring Biosensor
摘要： Real-time and high-sensitivity biosensors are urgently needed in biochemistry. As one of the candidates, silicon-on-insulator (SOI) sensors exhibits excellent performances. However, there are still some limitations to hinder them to be applied to much wider scenarios. Fabrication tolerance is also required for the generalization of these micro- or nano-structure. In this work, we demonstrate an SOI waveguide biosensor for biochemical sensing with high sensitivity of 1.88×105 dB/RIU. Because of the compact structure and low demand for accuracy of fabrication, this device possesses better applicability and reliability.
关键词： Nanophotonics,Biosensor,SOI,Microring
更新于2025-09-16 10:30:52