- 标题
- 摘要
- 关键词
- 实验方案
- 产品
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Effect of Dielectric Charging on Capacitance Change of an SOI Based CMUT
摘要： Effect of dielectric charging on the performance of SOI based Capacitive Micromachined Ultrasonic Transducers (CMUT) has been investigated. Measurements on an SOI based CMUT show that that the capacitance change as a function of DC bias is considerably higher than analytically calculated values. Investigation shows that this deviation in capacitance from analytically calculated values is due to the combined effects of different dielectric charging phenomena due to a strong electric field, trap charges in the SOI oxide layer, the charge motion associated with the leakage current through the buried oxide layer, and the air in the CMUT cavity. Additionally, this charging effect degrades the transduction efficiency as the induced polarization reduced the effective bias across the CMUT. It is concluded that the buried oxide (BOX) layers in SOI wafers are not suitable for use as dielectric spacers in electrostatic MEMS devices.
关键词： SOI,dielectric charging,Capacitance,microfabrication,MEMS,CMUT,leakage current
更新于2025-11-14 17:28:48
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Development of a new high-speed readout system for SOI pixel detectors
摘要： We are developing a new high-speed readout system for silicon on insulator (SOI) pixel detectors. The SOI detector is a monolithic radiation imaging detector based on a 0.2 μm FD-SOI CMOS process. Previously, we used a Xilinx Virtex-4/5 FPGA readout board for the SOI detector and developed many facilities for this board. However, the Virtex-4/5 FPGA is now obsolete and does not have sufficiently high performance for recent experiments that require more than 1-kHz high-speed imaging with a large number of pixels. Thus, we started to develop a new high-speed readout system using the KC705, which is the evaluation board for the Xilinx Kintex-7 FPGA. We developed a new data acquisition structure that has backward compatibility with the previous environment on this board and implements several functions for practical purposes such as micro Computed Tomography. The transfer speed achieved by the new system is 95.3 fps for a 426k pixel detector in continuous data-taking mode, and 762.5 fps in maximum-speed mode. The details of the new readout system are presented.
关键词： X-ray imaging,SOI,FPGA,DAQ,Pixel detector
更新于2025-09-23 15:23:52
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MoS2/silicon-on-insulator Heterojunction Field-Effect-Transistor for High-performance Photodetection
摘要： In this letter, we demonstrate a novel junction field effect transistor (JFET) by transferring MoS2 onto silicon-on-insulator (SOI) substrate to control the thin Si channel. By combining high light absorption coefficient in MoS2 with high internal gain in thin Si channel, the device can be used for photodetection and achieve high responsivity up to ~1.78×104 A/W, high detectivity over 3×1013 Jones, and short response time down to 1.44 ms. Furthermore, unlike conventional SOI photodetector which is only sensitive to UV light, the response spectrum of our proposed device peaks in visible/near-infrared region, which is interesting for imaging and optical communication applications.
关键词： SOI,High photoresponsivity,Van der Waals heterojunction,MoS2,Junction field effect transistor
更新于2025-09-23 15:22:29
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Analysis of Super-Steep Subthreshold Slope Body-Tied SOI MOSFET and its Possibility for Ultralow Voltage Application
摘要： In this paper, we review a super-steep subthreshold slope (SS) (< 1 mV/dec) body-tied (BT) silicon on insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) fabricated with 0.15 μm SOI technology and discuss the possibility of its use in ultralow voltage applications. The mechanism of the super-steep SS in the BT SOI MOSFET was investigated with technology computer-aided design simulation. The gate length/width and Si thickness optimizations promise further reductions in operation voltage, as well as improvement of the ION/IOFF ratio. In addition, we demonstrated control of the threshold voltage and hysteresis characteristics using the substrate and body bias in the BT SOI MOSFET.
关键词： body-tied,SOI,ultralow power,floating-body,steep subthreshold slope
更新于2025-09-23 15:22:29
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[IEEE 2018 33rd Symposium on Microelectronics Technology and Devices (SBMicro) - Bento Gon?alves, Brazil (2018.8.27-2018.8.31)] 2018 33rd Symposium on Microelectronics Technology and Devices (SBMicro) - Low-Frequency Noise Investigation in Long-Channel Fully Depleted Inversion Mode n-type SOI Nanowire
摘要： This work presents a Low-Frequency Noise (LFN) investigation in fully depleted n-type Silicon-On-Insulator (SOI) nanowire transistors working in linear region with VDS=50mV. Long-channel devices of 1μm and 10μm are evaluated. A wide range of fin width is considered in the LFN analysis, from 15nm up to 105nm. The results showed a flicker noise (1/fγ) behavior with gate voltage and a decrease of normalized noise SID/IDS overdrive increase for frequencies bellow 500Hz. Above this frequency, that generation and recombination noise with 1/f2 decay overlaps the flicker noise, becoming the predominant noise source. The cut-off frequency increases with gate voltage overdrive while the gamma exponent decreases. Gamma reduces from 1.3 to 0.9 and from 0.95 to 0.65 for devices with channel length of 1μm and 10μm, respectively. A major noise variation of about one order of magnitude with gate voltage overdrive increase was observed in devices of 1μm long in comparison to channel length of 10μm. The devices showed weak noise dependence on fin width due to mobility decrease as nanowires become narrower.
关键词： fully depleted SOI,low-frequency noise,nanowire
更新于2025-09-23 15:21:21
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[IEEE 2019 IEEE 2nd International Conference on Knowledge Innovation and Invention (ICKII) - Seoul, Korea (South) (2019.7.12-2019.7.15)] 2019 IEEE 2nd International Conference on Knowledge Innovation and Invention (ICKII) - A Physical Threshold Voltage Model of Nanoscale Ultra-thin Body Ultra-thin Box SOI MOSFETs with a Gaussian Doping Profile
摘要： An insightful study of the virtual cathode is performed for the nanoscale ultra-thin body ultra-thin box SOI MOSFETs with a vertical Gaussian doping. And the physical, compact threshold voltage model is derived based on an analytical solution of two-dimensional Poisson equation with the evanescent-mode analysis. The accuracy of the model has been verified by 2D numerical device simulations using Sentaurus Technology Computer-Aided Design (TCAD) from Synopsys. Applying the newly developed model, the threshold voltage sensitivities to channel length, silicon-film thickness, buried-oxide thickness, and the channel doping concentration have been comprehensively investigated. Good agreements are achieved. Model predictions indicate that the individual UTBB-SOI MOSFET with a non-uniform doping profile is feasible at 10 nm scale. This work has both theoretical and practical significance and provide aids in promoting theoretical modeling research and applications of new UTBB-SOI based devices.
关键词： UTBB-SOI MOSFET,Analytical model,Gaussian doping,Virtual cathode
更新于2025-09-23 15:21:01
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Investigation of the on-state behaviors of the variation of lateral width LDMOS device by simulation
摘要： In this paper, the main content revolves round the on-state characteristics of the variation of a lateral width (VLW) LDMOS device. A three-dimensional numerical analysis is performed to investigate the specific on-resistance of the VLW LDMOS device, the simulation results are in good agreement with the analytical calculation results combined with device dimensions. This provides a theoretical basis for the design of devices in the future. Then the self-heating effect of the VLW structure with a silicon-on-oxide (SOI) substrate is compared with that of a silicon carbide (SiC) substrate by 3D thermoelectric simulation. The electrical characteristic and temperature distribution indicate that taking into account the SiC as the substrate can mitigate the self- heating penalty effectively, alleviating the self heating effect and improving reliability.
关键词： self-heating effect,specific on-resistance,SOI,LDMOS transistor
更新于2025-09-23 15:21:01
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SET Sensitivity of Tri-Gate Silicon Nanowire Field-Effect Transistors
摘要： The SET response of SOI tri-gate silicon nanowires is investigated using direct measurements of current transients. Resulting collected charge distributions are compared to simulations in two steps: Monte-Carlo simulations of deposited energy and TCAD simulation of collected charge, using detailed description of charge generation. Good agreement with experimental data is obtained. Current simulation tools can thus be used, with minor optimization, to simulate such integrated devices. The analysis of SETs show collected charge values lower than both the charge estimated from the LET and the charge actually generated in the nanowire, revealing a limited sensitivity of nanowire devices to high LET ions.
关键词： Nanowire,SEE,Single-Event Transient,Ultra-Thin SOI,Particle-matter interaction,Single-Event Effect,Geant4,FinFET,TCAD,Multiple-gate,Simulation,SET,Experiments
更新于2025-09-23 15:21:01
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Simulation of structural design with high coupling efficiency in external cavity semiconductor laser
摘要： For external cavity semiconductor lasers (ECSLs), high coupling efficiency is critical to reducing the linewidth. In this paper, the coupling efficiency between the laser diode and the waveguide grating has been improved, with proposals for its improvement presented, including adding spot-size conversion (SSC) and using a silicon-on-insulator (SOI) waveguide. The results indicate an increase of coupling efficiency from 41.5% to 93.1%, which exhibits an improvement of approximately 51.6% over conventional schemes. The relationship between coupling efficiency and SOI waveguide structures is mainly concerned in this article. These findings provide a new way for the future research of the narrow linewidth of ECSL.
关键词： SOI waveguide,coupling efficiency,spot-size conversion
更新于2025-09-23 15:19:57
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[IEEE 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Rome, Italy (2019.6.17-2019.6.20)] 2019 PhotonIcs & Electromagnetics Research Symposium - Spring (PIERS-Spring) - Generating and Steering of Quasi-nondiffraction Beam by Substrate Integrated Waveguide Slot Array Antenna
摘要： This paper presents a physics-based compact modeling approach that incorporates the impact of total ionizing dose (TID) and stress-induced defects into simulations of metal-oxide-semiconductor (MOS) devices and integrated circuits (ICs). This approach utilizes calculations of surface potential (ψs) to capture the charge contribution from oxide trapped charge and interface traps and to describe their impact on MOS electrostatics and device operating characteristics as a function of ionizing radiation exposure and aging effects. The modeling approach is demonstrated for bulk and silicon-on-insulator (SOI) MOS device. The formulation is verified using TCAD simulations and through the comparison of model calculations and experimental I-V characteristics from irradiated devices. The modeling approach is suitable for simulating TID and aging effects in advanced MOS devices and ICs, and is compatible with modern MOSFET compact modeling techniques. A circuit-level demonstration is given for TID and aging effects in SRAM cells.
关键词： MOSFET,SOI,semiconductor devices,compact modeling,ionizing radiation,Aging effects
更新于2025-09-23 15:19:57