- 标题
- 摘要
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- 实验方案
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Detection limit of a VCO based detection chain dedicated to particles recognition and tracking
摘要： A particle detection chain based on CMOS-SOI VCO circuit is presented. The solution is used for the recognition and the tracking of a given particle at circuit level. TCAD simulation of the detector has been performed on a 3x3 matrix of diodes based detector for particles recognition and tracking. The current response of the detector has been used for a case study in order to determine the ability of the chain to recognize an alpha particle crossing a 3x3 detection cell. The detection limit of the proposed solution is investigated and discussed in this paper.
关键词： TCAD simulation,VCO,particle detector
更新于2025-09-23 15:23:52
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Research of Single-Event Burnout and Hardening of AlGaN/GaN-Based MISFET
摘要： This brief ?rst time presents single-event burnout (SEB) simulation results for conventional AlGaN/GaN gate ?eld plate MISFET (GFP-C MISFET), simultaneously, a hardened MISFET with electrode connected doped plugs in the buffer (EC-DP MISFET) is proposed for the ?rst time. The SEB triggering mechanisms contain the back-channel effect and following impact ionization dominated by electron in the high ?eld region. By comparing the simulation results from the GFP-C MISFET and proposed hardened EC-DP MISFET, the carriers induced by heavy ion can be quickly absorbed to drain and source electrode through EC-DP, so that the proposed EC-DP MISFET can achieve better SEB performance than conventional one. With a heavy ion having the linear energy transfer value of 0.6-pC/μm striking vertically, SEB threshold voltage obtained in GFP-C MISFET and hardened EC-DP MISFET is 280 and 338 V, respectively.
关键词： MISFET,single-event burnout (SEB) hardening,SEB,technology computer-aided design (TCAD),Electrode connected doped plugs (EC-DP)
更新于2025-09-23 15:23:52
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Simulation-Based Sensitivity Analysis of Conduction and Switching Losses for Silicon Carbide Power MOSFETs
摘要： The behavior of silicon carbide power MOSFETs is analyzed using TCAD device simulations with respect to conduction and switching losses. Device designs with varying breakdown voltages are simulated. The contributions to the on-state resistance are shown at room and elevated temperature. Whereas channel and substrate resistance dominate at low breakdown voltages, drift and JFET resistance dominate at high breakdown voltages. With increasing temperature, the channel resistance decreases and thus the drift resistance is the main contributor already at medium breakdown voltages. Manufacturing processes of a device can have a high influence on its losses. Variations in interface mobility, drift doping, and p-body doping can lead to a significant change of on-resistance, internal capacitances, and reverse recovery charge. For higher voltage classes the drift layer properties should be of major interest as it influences on-resistance and reverse recovery charge.
关键词： SiC power MOSFET,TCAD device simulation,sensitivity analysis,losses
更新于2025-09-23 15:23:52
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[IEEE 2018 19th International Conference on Electronic Packaging Technology (ICEPT) - Shanghai (2018.8.8-2018.8.11)] 2018 19th International Conference on Electronic Packaging Technology (ICEPT) - Effect of oxide layers on MONOS device performance based on TCAD simulation
摘要： 3D NAND flash memory based on MONOS structure offers a new path to break through the limitation of memory capacity of 2D NAND flash. Thickness of top oxide layer and bottom oxide influence device performance. Technology Computer Aided Design(TCAD), as the most effective and powerful tool to study the electrical properties of various semiconductor devices, can be used to reveal the influence. In this paper, P/E cycle of MONOS device with varied thickness of high-k aluminum oxide and tunneling layer are investigated with Fowler-Nordheim tunneling model being put into consideration. Furthermore, threshold voltage and data retention of MONOS device with optimized thickness of oxide layers are characterized as well, which leave a novel route for related device design and optimization.
关键词： TCAD,Oxide layers,3D NAND,Data retention
更新于2025-09-23 15:22:29
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[IEEE 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Austin, TX (2018.9.24-2018.9.26)] 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - A versatile harmonic balance method in a parallel framework
摘要： In this paper, we present a parallelized and versatile harmonic balance approach for modeling the small-signal and large-signal frequency-domain response of the coupled semiconductor drift-diffusion equations used in TCAD device simulations. Our approach begins with a time-domain TCAD code, and we describe the process to adapt the system into the frequency domain so that the transformation can be parallelized. Both small-signal and large-signal analyses are easily simultaneously incorporated. Furthermore, we introduce the Isofrequency Remapping Scheme, so that an arbitrary number of high frequencies can be analyzed without introducing a prohibitive expense. Results obtained by our small-signal and large signal harmonic balance methods are shown to capture the same response for a linear device, as expected. Further results use our harmonic balance method to explore a prohibitively expensive time-domain problem: a large-signal, two-tone simulation too costly for a time-domain analysis, for which we are able to produce the expected response with intermodulation.
关键词： TCAD,parallelization,frequency-domain analysis,frequency mapping method,harmonic balance method
更新于2025-09-23 15:22:29
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[IEEE 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - Austin, TX, USA (2018.9.24-2018.9.26)] 2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) - The efficient DTCO Compact Modeling Solutions to Improve MHC and Reduce TAT
摘要： This paper introduces the recent modeling challenges of the Process Development Kit (PDK) development due to the limitations of transistor scaling and the impact of new process technologies. And a new modeling solution, Agile PDK is presented to break though these development challenges by enabling the Design Technology Co-Optimization (DTCO) activities in the manufacturing levels. A series of advanced algorithms are newly introduced to not only reduce the PDK development time (TAT), but also improve the model accuracies and Model-to-Hardware Correlation (MHC). It is applied to the latest DRAM technology and dramatically reduces development TAT up to 50% with improved model accuracies.
关键词： PDK,DTCO,Regression,SPICE Models,MHC,Full binning,TCAD TEG,API,Optimization
更新于2025-09-23 15:22:29
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Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs
摘要： In nanoscale fully depleted silicon-on-insulator (FD-SOI) MOSFETs, the standard deviation of threshold voltage (σVth) caused by random dopant fluctuation (RDF) is an important parameter to predict the performance of transistors and circuits. In this paper, an analytic model of σVth considering both the dopant 'number' and dopant 'position' fluctuation in channels is proposed. A new model of σVth,num caused by 'number' is given and the method of obtaining the 'position' influence ratio Rp is discussed in this paper. Moreover, the simulation methods are analyzed in detail. The calculated σVth values in FD-SOI MOSFETs are compared with the Sentaurus TCAD simulation results at different channel lengths, channel doping concentrations, SOI film thicknesses, front gate oxide thicknesses, and buried-oxide thicknesses. The comparison shows that the proposed model matches well with the obtained numerical simulation results.
关键词： threshold voltage variation,analytical model,fully depleted silicon-on-insulator MOSFETs,Sentaurus TCAD simulation,random dopant fluctuation
更新于2025-09-23 15:22:29
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Designing Beveled Edge Termination in GaN Vertical p-i-n Diode-Bevel Angle, Doping, and Passivation
摘要： A series of electric field profile simulations in gallium nitride (GaN) p-i-n vertical diodes with negative bevel termination is carried out to optimize the bevel design. The bevel angles are varied from 90? to 0.1? with reasonably small increments to study the impact of the bevel angle on the electric field profile. The doping densities are also varied to study a more generalized trend; a new parameter defined as transition angle θt is proposed to characterize the effectivity of a beveled edge termination. Considering the potential dry etch damage on the bevel side-wall during device fabrication, the fixed surface charge from the dangling bonds and commonly used dielectric passivation are also added separately to investigate their influence. This article presents a comprehensive simulation study of GaN p-i-n diode with negative beveled edge termination, making it a useful guide for designing a simple and effective beveled edge termination, which eventually helps to enable the routine avalanche in GaN p-i-n diodes.
关键词： beveled edge termination,surface charge,simulation,gallium nitride (GaN),transition angle,silvaco,passivation,p-i-n diode,Avalanche,TCAD
更新于2025-09-23 15:21:01
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A compact model and TCAD simulation for GaN-gate injection transistor (GIT)
摘要： Wide bandgap (WBG) semiconductor devices represent an attractive developing technology for power applications that is recently gaining commercial ground. GaN has advantages as one of the top contenders with high bandgap, high mobility, high saturation velocity, and high breakdown voltage. GaN enhancement-mode devices are favored over depletion-mode devices for power electronics applications and are only recently becoming commercially available. The enhancement-mode device investigated in this work is a GaN-gate injection transistor (GIT) in which the normally-off operation is achieved with an additional p-doped gate. This paper presents current-voltage (I-V) characteristics of GaN-GIT device using a physics based compact model as well as TCAD (Technology Computer-Aided Design) numerical simulation to predict and model the device behavior of the GIT. This paper presents a comparison of the TCAD simulation results with a compact model intended for low frequency applications in power electronics in the KHz to MHz range.
关键词： GIT,GaN,WBG,TCAD,HEMT
更新于2025-09-23 15:21:01
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Simulation of 3D-Silicon sensors for the TIMESPOT project
摘要： The experimental conditions in future High Luminosity LHC experiments require new detector systems with increased performances compared to the current state of the art. In this context, increasing spacial resolution and including time measurement with a resolution of less than 50 ps for particle tracking systems can avoid false track reconstruction due to event pileup. For this kind of future tracking detectors the 3D silicon sensor technology appears as a good option. In this context the TIMESPOT initiative was launched. Concerning the development of the sensor, different geometrical solutions have been explored and simulated to optimize the timing response of the single pixel sensor using Sentaurus TCAD. The configuration with the best electric field characteristics for timing was selected for signal simulation. In order to compensate the very time-consuming behavior of TCAD simulations, a faster charge transport simulator with TCAD and Geant4 support is under development. Further sensor configurations, including a first primitive capacitive and resistive load, were also simulated and evaluated. This paper shows a general overview of the project with particular attention to the silicon sensor development. First results are presented.
关键词： Fast timing tracking,3D silicon sensors,Tracking detectors,sensor simulation,TCAD
更新于2025-09-23 15:21:01