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A monolithically integrated micro-LED display based on GaN-on-Silicon substrate
摘要： A monolithic micro-light-emitting-diode (LED) display technology was proposed using a gallium-nitride-on-silicon substrate. An active matrix (AM) display was realized by interconnecting nitride-based LEDs as display pixels with silicon (Si) thin-film-transistors (TFTs) as driving circuitries. Metal-oxide semiconductor TFTs were fabricated on Si surface which had been exposed after the dry etching of LED epitaxial layer. The mobility and sub-threshold slope were measured as 354.3 cm2/Vs and 0.64 V/dec, respectively. A 150 pixel-per-inch 0.6-inch monolithic display was demonstrated with a 60 x 60 pixel-array AM display by an integration technology on the same substrate.
关键词： micro-LED,monolithic integration,active matrix display,GaN-on-Silicon
更新于2025-09-12 10:27:22
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III–V nanowire array telecom lasers on (001) silicon-on-insulator photonic platforms
摘要： III–V nanowires have recently gained attention as a promising approach to enable monolithic integration of ultracompact lasers on silicon. However, III–V nanowires typically grow only along h111i directions, and thus, it is challenging to integrate nanowire lasers on standard silicon photonic platforms that utilize (001) silicon-on-insulator (SOI) substrates. Here, we propose III–V nanowire lasers on (001) silicon photonic platforms, which are enabled by forming one-dimensional nanowire arrays on (111) sidewalls. The one-dimensional photonic crystal laser cavity has a high Q factor >70 000 with a small footprint of (cid:2)7.2 (cid:3) 1.0 lm2, and the lasing wavelengths can be tuned to cover the entire telecom bands by adjusting the nanowire geometry. These nanowire lasers can be coupled to SOI waveguides with a coupling ef?ciency > 40% while maintaining a suf?ciently high Q factor (cid:2)18 000, which will be bene?cial for low-threshold and energy-ef?cient operations. Therefore, the proposed nanowire lasers could be a stepping stone for ultracompact lasers compatible with standard silicon photonic platforms.
关键词： monolithic integration,III–V nanowires,telecom lasers,photonic crystal laser cavity,silicon photonic platforms
更新于2025-09-12 10:27:22
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[IEEE 2019 Second International Workshop on Mobile Terahertz Systems (IWMTS) - Bad Neuenahr, Germany (2019.7.1-2019.7.3)] 2019 Second International Workshop on Mobile Terahertz Systems (IWMTS) - Endfire Transition from Coplanar Waveguide-to-WR3 Rectangular Waveguide for Monolithic Integration with THz Photodiodes
摘要： In this paper, an endfire transition from coplanar-to-rectangular waveguide (CPW-to-WR3) for operation in the WR3-band (220-320 GHz) is presented. The transition is designed for providing connectivity between a monolithically integrated InP-based terahertz photodiode (PD) to a WR3 rectangular waveguide. The presented transition is based on a CPW-fed planar dipole antenna designed on InP substrate which placed in the E-plane of the rectangular waveguide. The dipole-based transition converts the direct coupled quasi-TEM CPW mode of the PD output to the TE10 mode of the rectangular waveguide. The proposed design provides a simple approach avoiding complex integration and packaging techniques like air bridges, ribbon-bonds, or via holes. Numerical analysis of the designed transition shows a wideband performance with a 3 dB insertion loss (IL) over 88 GHz bandwidth and a 10 dB return loss (RL) over 53 GHz bandwidth within the WR3-band.
关键词： monolithic integration,Coplanar waveguide (CPW),WR3-band,THz photodiode.,endfire transition
更新于2025-09-12 10:27:22
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Monolithically Integrated GaN LED/Quasi-Vertical Power U-shaped Trench-gate MOSFET Pairs using Selective Epi Removal
摘要： We report on the demonstration of monolithically integrated light-emitting diode (LED) and quasi-vertical U-shaped trench-gate metal-oxide-semiconductor field-effect transistor (UMOSFET) in GaN. Selective epi removal (SER) approach was used on an LED-on-FET epi stack on sapphire substrates. Individual p-GaN layers were used for LED and FET in our design. LED light modulation by the supply voltage and the FET gate voltage was realized, and an integrated 350μm×350μm LED/UMOSFET pair exhibits a light output power (LOP) of 4.9 W/cm2 or 6.0 mW. An integrated device with a UMOSFET driving a 3-LED chain was also demonstrated. The normally-off power UMOSFET has a threshold voltage of 7 V, a breakdown voltage of 208 V, and a specific on-resistance of 23 mΩ-cm2, in which hexagonal cells were applied to obtain identical m-plane MOS gate interfaces. The effect of FET sizing on integrated pairs was also studied, and a trade-off model of FET/LED power ratio vs. FET/LED area ratio was created, which serves as universal criterion for FET/LED integration. The tested device with the best trade-off has FET/LED area ratio of 24% and FET/LED power ratio of 56%. This work creates a new building block for future GaN light-emitting integrated circuits (LEICs).
关键词： monolithic integration,FET/LED power ratio vs. area ratio trade-off,quasi-vertical power UMOSFET,LED,GaN
更新于2025-09-12 10:27:22
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<i>(Invited)</i> Monolithic Integration of Si-CMOS and III-V-on-Si through Direct Wafer Bonding Process
摘要： Integration of Si-CMOS and III-V compound semiconductors (with device structures of either InGaAs HEMT, InGaP LED, GaAs HBT, GaN HEMT or InGaN LED) on a common Si substrate is demonstrated. The Si-CMOS layer is temporarily bonded on a Si handle wafer. Another III-V/Si substrate is then bonded to the Si-CMOS containing handle wafer. Finally, the handle wafer is released to realize the Si-CMOS on III-V/Si substrate. For GaN LED or HEMT on Si substrate, additional wafer bonding step is required to replace the fragile Si (111) substrate after high temperature GaN growth with a new Si (001) wafer to improve the robustness of the GaN/Si wafers. Through this substrate replacement step, the bonded wafer pair can survive the subsequent processing steps. The monolithic integration of Si-CMOS + III-V devices on a common Si platform enables new generation of systems with more functionality, better energy efficiency, and smaller form factor.
关键词： III-V compound semiconductors,Si-CMOS,wafer bonding,HEMT,GaN LED,monolithic integration
更新于2025-09-10 09:29:36
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[IEEE 48th European Solid-State Device Research Conference (ESSDERC 2018) - Dresden (2018.9.3-2018.9.6)] 2018 48th European Solid-State Device Research Conference (ESSDERC) - InGaAs FinFETs 3D Sequentially Integrated on FDSOI Si CMOS with Record Perfomance
摘要： In this paper, we demonstrate InGaAs FinFETs 3D sequentially (3DS) integrated on top of a fully-depleted silicon-on-insulator CMOS. Top layer III-V FETs are fabricated using a Si CMOS compatible HKMG replacement gate flow and self-aligned raised source-drain regrowth. The low thermal budget of the top layer process caused no performance degradation of the lower level FETs. Record ION of 200 μA/μm (at IOFF = 100 nA/μm and VDD = 0.5 V) for 3DS integrated III-V FETs on silicon is demonstrated, with a 50% reduction of RON compared to previous work. The achieved improved performance can be attributed to the introduction of doped extensions underneath the gate region as well as improvements in the direct wafer bonding technique.
关键词： 3DS,monolithic integration,wafer bonding,III-V,sequential integration,FinFETs
更新于2025-09-04 15:30:14